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Home | Home Japanese | Sessions and Keynotes | Author's Info | Download
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IBM Corporation, NY, USA System Scaling Technology Design Department Manager 3 Dimensional Memory
Semiconductor technology has scaled successfully for 30 years enablingtoday's Peta-Flop super computing. However, scaling has become increasingly difficult and expensive, and while post-Si CMOS technologies may some day overcome current challenges, they are still in the early phase of research. This talk will describe orthogonal scaling through the 3D memory development. We will review the evolution of semiconductor scaling including SOI, FIN, and embedded DRAM solution for high-performance logic technology. We will then explain the 3D stacking of embedded DRAM cache prototypes using Through-Silicon-Vias (TSV) and review today's Hybrid-Memory Cube (HMC) and High-Banwidth Memory (HBM) modules targeting high-performance main memory applications. Final comments on the challenges for 3D memory using wafer-scaling 3D integration will conclude the talk.
Taiwan Semiconductor Manufacturing Co., Ltd. (TSMC), Taiwan Director of 3DIC/IIPD Division 3DIC Technology – CoWoS as an Example
3D IC is a highly anticipated technology to enhance the overall chip performance and to achieve heterogeneous system integration by way of three-dimensional chips stacking using through-silicon-vias (TSV). Today, most of the technology barriers of 3D IC, from process standpoint, have been overcome, and products with fine-pitch TSV are recently demonstrated. However, the extensive use of this technology still depends on factors, such as the availability of stacked memory, design ecosystem, test methodology, thermal solutions and cost. In particular, challenges in heterogeneous chip integration involve dies from different sources, and, possibly, complicated chip-package-interaction (CPI) is needed to be resolved. CoWoS technology is a simplified 3D IC integration supply chain, which is able to quickly improve and stabilize the overall yield, and reduce the reliability risks. The technology is ideal for thin wafer integration flow, as the thin TSV wafer is always protected. The wafer level integration minimizes warpage, which is critical for μ-bump stacking yield and reliability. The advantages of CoWoS get better for larger size chips. The design reference flow is deployed, and full design methodology and kits are ready. The CoWoS technology passed package and product qual on multiple products, and achieved excellent yield in production.
Chris Bailey
Power electronics covers various disciplines, especially semiconductor, circuit design, thermal design (heat transfer, fluid flow), electromagnetics (EMI, Inductors, transformers), digital electronics, control theory, and materials science in the context of packaging and reliability engineering. It also covers a wide range of power (mW to MW), temperature (-55C to 275C), frequencies (DC to GHz) and dimensions (um to km). This presentation will discuss traditional packaging technologies for power electronics modules such as IGBT’s where both wire bonding and solder bonding technologies have been used. In addition the presentation will detail new bonding technologies such as low process temperature bonding techniques (e.g. silver sintering and transient liquid phase bonding). Challenges with regards the use of these bonding technologies on overall module reliability will be discussed both for silicon devices and wide band gap devices such as silicon carbide.
Mark S Goorsky
Wafer Bonding Technologies for Photovoltaic and Other Energy Aapplications
Recent achievements in photovoltaic solar cell record efficiencies have been achieved using wafer bonding techniques. Here, we discuss a low thermal budget process to achieve high electrical and thermal conductivities across III-V bonded interfaces using sulfur-based passivation techniques. We have determined several interesting properties of these bonded interfaces: (i) any pre-existing planar oxide (e.g., for GaAs) at the bonding interface migrates to form three dimensional-sphere-like structures at very low temperatures (< 400 °C); (ii) high electrical conductivity bonds across GaAs-like interfaces and InP-like interfaces are achieved during temperatures that are necessary for ohmic alloying steps (400 °C – 600 °C, minutes) and (iii) the relative orientation of the lattice planes on either side of the bond influence the conductivity across the interface. These results have led to an understanding of the thermal and electrical stability of III-V bonded interfaces and guide the way for the incorporation of II-V materials in other energy applications as well as power and logic applications.
M. Jamal Deen
Nanobonding - A Key Technology for Emerging Applications in Health and Environment
Heterogeneous integration of electronic, photonic, optical, fluidic and mechanical components is urgently needed for real-world health and environmental applications. However, integration of these diverse technologies into a single packaged system is a very challenging task. In such integrated systems, further challenges appear from the requirements of maintaining the performance of the components with high reliability, and without heating or pressure during the integration process. To address the integration issues, we have established the unique Micro- and Nano-Systems Laboratory (MNSL) at McMaster University. In this presentation, we will introduce the MNSL with a focus on our processing and integration capabilities, and will also briefly describe our characterization facilities. The nanobonding technologies we are pursuing provide void-free, strong, and nanoscale bonding at room temperature or at low process temperatures, and do not require chemicals, adhesives, or high external pressure. With this nanobonding as a key enabling technology, we will discuss several examples of the integration of various soft and hard materials such as silicon, silicon carbide, germanium, gallium arsenide, glass, polymers and gratings. These substrates are being used to create, for example, electronic (silicon), photonic (silicon and gallium arsenide), micro-electro-mechanical (glass and silicon) and fluidic (silicon and glass and PDMS and SU-8) components for our biosensing and bioimaging systems. Details of some of these systems – a low-cost, high performance miniaturized biosensing system for pathogen detection, a biophotonic imaging system for the screening and early detection of tumors or cancers, and a micro-Raman system for environmental applications will be presented and discussed.
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