Home | Home Japanese | Sessions and Keynotes | Author's Info | Download
Program | Social Event | Hotel | Location | Registration
Committee | Sponsors | Contact


The University of Tokyo
GMSI (Global Center of Excellence for Mechanical Systems Innovation)Open seminar
Lectures for graduate students at the School of Engineering, The University of Tokyo

DATE: 21st May 2010
PLACE: Food Science Building 1F, Faculty of Agriculture, MAP #116

13:30-15:30
Low Temperature Direct Wafer Bonding: Mechanisms and Applications


Dr. Hubert Moriceau
CEA, LETI, 38054 Grenoble - France

Direct wafer bonding processes are more and more attractive to achieve stacking structures. Some processes have been already implemented in industrial applications for several years. The most well known application is the mass production of silicon on insulator (SOI) bonded structures performed thanks to the Smart Cut™ technology. Recent advances have led to the emergence and development of direct-bonded structures suitable for an attractive field of innovative applications. In a generic approach, direct wafer bonding consists in contacting two wafer surfaces without any additional adhesive in between. Considering contacts by adhesive asperities at a micrometre or nanometre scale have led to the emergence of bonding models associated to statistical descriptions of surfaces. Si or SiO2 direct bonding have been widely studied for more than 20 years and widely applied in the SOI wafer fabrication. When performed with other materials, either surface preparations have to be tuned or surfaces can be capped by bonding layers. Nowadays, many hetero-structures are successfully obtained by direct wafer bonding, in which at least one wafer can be thinned down to a few micrometers depending on applications. An overview on mechanisms and results of direct bonding will be mainly focused on Si or SiO2 bonding processes. Recent developments will be presented for achievements of innovative bonded structures suitable for new applications in microelectronics, microtechnologies, sensors, MEMs, optical devices, biotechnologies, 3D-integration….


15:50-17:50
3D Integrated Circuit Technology—A Historical Perspective on How We Got Here and Where We May Be Heading

Dr. Lisa McIlrath
President & CEO, R3Logic, Inc.
Bedford, MA 01730 USA

Much like the Field Effect Transistor (FET), first patented in 1925, “three-dimensional” IC prototypes were built long before the technology had any hope of commercial viability. The first known 3D circuit was built at least as early as 1967, but until as recently as 2007, few people were confident that 3D technology would take hold. The semiconductor industry has known many “great ideas” that have never made it to commercial success and were subsequently forgotten. What was different about 3D? In this seminar we will take a historical look at developments, both in the process technology and in the design concepts that propelled 3D research forward during its years as, well, a bit of a joke. Then, in the late 90’s – early 00’s there came the perfect storm of failed technology initiatives, which left 3D integration as the only candidate left standing to get more out of Moore. We will review the different types of 3D integration technology that have been developed, who the major players are and what issues and applications have driven the technology choices. Excitingly, we are on the verge of seeing major foundries open 3D fabrication lines, and within a few years, it will be as available as CMOS technology is today. We will explore some applications in micro- and nano-technology that may be enabled by these events.