Helmut BAUMGART: Strain Engineered Silicon-on-Insulator (sSOI) Technology by Wafer Bonding and Layer Transfer
This presentation aims to provide an overview of wafer bonding for strain engineered Silicon-on-Insulator (sSOI) Technology and some of the properties and applications. The International Technology Roadmap for Semiconductors (ITRS) is calling for innovation in materials and device structures to sustain continued CMOS device scaling according to Moore’s Law. Due to aggressive scaling mobility enhancements become key to maintaining transistor performances. Stresses are known to affect bandgap and mobility in Silicon. For the upcoming generation of 45nm devices and beyond, Si technology will depend on locally strained FET channels to deliver next node performance. SOI technology offers CMOS performance enhancement with the use of an embedded oxide layer to isolate transistors from the substrate, which results in lower parasitic capacitance and reduced junction leakage. Combining SOI substrates with strained Si technology takes advantage of the performance enhancement by both SOI and the increased carrier mobility of strained Si. There are two main approaches in producing mobility enhancement: strain engineering and surface orientation effects. The method of choice for strain engineering is to epitaxially grow a Si1-xGex layer on a Si substrate. The strain originates from the differences in lattice spacing between Si and SiGe. By selectively choosing the Ge doping content of Si1-xGex, one can modulate the built-in strain level. Subsequently, a thin bi-axially tensile strained Si layer can be grown epitaxially on top of a strain relaxed Si1-xGex buffer layer in order to obtain a strained Si epitaxial device layer. In this composite fabrication scheme the thin film epitaxial process steps are followed by bonding and layer transfer to a dielectrically insulated handle wafer to generate device-grade sSOI wafers.
Wafer Bonding can take advantage of the fact that hole mobility of p-channel MOSFETs is 2.5 times higher on (110) oriented surfaces compared with standard wafers of (100) orientation. Electron mobility is highest on (100) oriented Si substrates. Wafer bonding technology lends itself naturally to fabricate hybrid substrates with different crystal orientations to take full advantage of carrier mobility dependence on wafer surface orientation and on geometrical preferences. This approach stacks vertically multiple layers of active devices on different orientations in a 3-D fashion. The concept of stacking device layers by wafer bonding can be extended to fabricate hybrid photonic/ electronic circuits. In recent years Wafer Bonding and SOI Technology have proven to be an advantageous materials platform for fabricating next generation double-gate and multi-gate 3-D devices. Promising results with 3-D devices have been obtained by various R&D laboratories worldwide. Such novel 3-D devices have the potential to extend Moore’s Law beyond classical planar Si technology. Wafer Bonding and Layer Transfer is expected to be a key enabling technology and strained
Dorota TEMPLE: Overview of 3-D Integration Technology
Low temperature bonding is a critical enabler in the rapidly developing field of 3-D integration technology in which separate, individually complete device layers are thinned, bonded and interconnected through vertical interconnects with lengths typically on the order of just tens of microns. The 3-D integration technology provides a way to build complex microsystems without compromising the system performance and fabrication yield. This talk will give an overview of different technology approaches, key process techniques and applications which motivate the technology development.
Joerg BAGDAHN : Mechanical Reliability of Wafer-Bonded Microsystem
Experimental and theoretical approaches are presented, which can be applied to characterize the mechanical reliability properties of wafer-bonded microsystems. Those approaches can be used during the development of bonding technologies, for yield improvement during fabrication and failure analysis as well as for the reliability assessment of micromechanical sensors and actuators. Typical failure mechanism like stress corrosion effects, which can lead to a delayed failure of wafer-bonded interface, will be discussed. Special attention is given to low temperature bonding technologies, which are frequently used for bonding of microsystems.
Hubert MORICEAU : Low temperature direct bonding processes: attractive ways for 3D device integrations
Direct bonding technologies are very attractive ways to stack wafers to wafers or dies to wafers, in a wide field of applications as microelectronics, sensors, biologics or 3D device integrations. Direct bonding can be carried out under various atmospheres or under vacuum and, most of the time, thermal treatments are applied to strengthen the bonds. However, bonding processes have to take into an account that some bonded structures could suffer of thermal treatments made at a too high temperature. Thus low temperature bonding processes have been pushed to address this issue. Surface activations, based either on plasma treatment or on chemical mechanical planarisation, have been mainly explored. Basic mechanisms involved in such surface activations will be described. Moreover results obtained by these low temperature bonding processes with various semiconductor, dielectric, metal and polymer surfaces will be shown to illustrate some potential applications in microelectronics or in 3D device integrations.
Manfred Reiche: Low-Temperature Bonding Processes
There are different techniques of wafer bonding to numerous applications. Today, wafer bonding is a key technology to realize different types of 3-dimensional micro-electromechanical systems (MEMS). It is also applied to combine different materials as for advanced substrates used in modern CMOS and other technologies. The application of heterogeneous materials and the process compatibility require only low-temperature processes during the bonding. Therefore, different bonding techniques were recently introduced allowing the formation of high bond energies even at annealing sequences below 500°C. For instance, additional interface layers such as patternable materials (SU-8, BCB, or other types of photoresist), low-temperature oxide layers (TEOS, SOG), and PE-CVD-layers (amorphous silicon, oxide, nitride) were used. Additional interface layers reduce the temperature range for further processes (as for photoresists), or are not applicable by different reasons (surface topography, sources for impurities, etc.). Furthermore, additional process steps are required as the CMP polishing of PE-CVD layers. Alternative techniques for low-temperature wafer bonding use the activation of the wafer surfaces before bonding. First wet chemical processes were applied result in an increase of the bond energy by a factor of about 2. On the other hand, higher bond energies were obtained by surface activation using plasma processes. Especially treatments in an oxygen plasma are most common, where different plasma sources were applied (RIE, ICP, ECR, or microwaves). Recently, also dielectric barrier discharges (DBD) were applied resulting in increased bonding strengths as reported for the low-pressure plasma activation.
The lecture deals with an overview about the existing low-temperature bonding techniques. Basic physical and chemical interface processes are discussed.
Piet MOOR: 3D integration technology developments at IMEC
IMEC is focusing its 3D-integration technology developments in 3
distinct directions: 3D-System-in-a- Package (3D-SiP),
3D-Wafer-Level-Packaging (3D-WLP) and 3D-Stacked-IC (3D-SiC). First,
the background of these separate approaches will be given and the
roadmap for the 3D-integration at IMEC will be presented. Next the
technologies involved, the typical characteristics and the ongoing
developments and results will be discussed in detail, focusing on the
assembly processes including flip-chip and collective bonding using e.g.
Cu thermocompression bonding and the combination of polymer and Cu
thermocompression bonding. As IMEC is also developing sensor systems
including MEMS, examples of zero-level packaging of MEMS using wafer
bonding will be discussed.
Makoto Yoshimi : Development of SOI Device Technology and Wafer Bonding by Smart Cuti
SOI (silicon-on-insulator) technology is nowadays widely used as a mainstream technology in MPUs, low-power ASICs, high-voltage ICs, and so on. In the first half of this presentation, the development history of SOI technology is reviewed, and the role that Smart Cut technology played is discussed. It is shown that, after the floating-body effect became no more a critical issue with the reduction of supply voltage in LSI systems to less than 2 V, how to get high-quality SOI wafers remained as the major issue to be solved. Smart Cut provided the solution by a unique method using wafer bonding and hydrogen implantation. In the second half, it is shown that Smart Cut can be applied to a variety of materials and structures, contributing not only to pushing the scaling limit of CMOS, but also adding LSIs enhanced performance and new functionalities. SOI wafer technologies for next-generation CMOS structures, such as strained-Si, ultra-thin film fully-depleted device, hybrid orientation channel, FinFET, etc., are introduced, along with application to capacitor-less DRAM and CMOS image sensor. Also, it is shown that SOI technology by wafer bonding can change the system architecture in future LSIs by applying to integrated photonics circuits.
